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freescale semiconductor data sheet: product preview document number: mpc5553 rev. 2, 03/2007 contents ? freescale semiconductor, inc., 200 7 . all rights reserved. this document provides electrical specifications, pin assignments, and package diagrams for the mpc5553 microcontroller device. for functional characteristics, refer to the mpc5553/mpc5554 microcontroller reference manual . 1 overview the mpc5553 microcontroller (mcu) is a member of the mpc5500 family of micr ocontrollers built on the power architecture? embedded technology. this family of parts contains ma ny new features coupled with high performance cmos technology to provide substantial reduction of cost per feature and significant performance improvement over the mpc500 family. the host processor core of th is device complies with the power architecture embedded category that is 100% user-mode compatible (with fl oating point library) with the original power pc? user instruction set architecture (uisa). the embedded architecture has enhancements that improve the performanc e in embedded applications. this core also has additi onal instructions, including digital signal processing (d sp) instructions, beyond the original power pc instruction set. this family of parts 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . 6 3.3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 electromagnetic interference characteristics . . . . . 9 3.5 esd characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 vrc/por electrical specifications . . . . . . . . . . . . 10 3.7 power-up/down sequencing . . . . . . . . . . . . . . . . 11 3.8 dc electrical specifications. . . . . . . . . . . . . . . . . . 13 3.9 oscillator and fmpll electr ical characteristics . . 20 3.10 eqadc electrical characteristics . . . . . . . . . . . . . 22 3.11 h7fa flash memory electr ical characteristics . . . 23 3.12 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 fast ethernet ac timing specifications . . . . . . . . 46 4 mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.1 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2 package dimensions. . . . . . . . . . . . . . . . . . . . . . . 56 mpc5553 microcontroller data sheet by: microcontroller division
mpc5553 microcontroller data sheet, rev. 2.0 overview freescale semiconductor 2 contains many new features couple d with high performance cmos te chnology to provide significant performance improvement over the mpc565. the mpc5553 of the mpc5500 family has two levels of memory hierarchy. the fa stest accesses are to the 8-kilobyte unified cache. the next level in the hierarchy contains the 64-kilobyte on-chip internal sram and 1.5 mbyte internal flash memory. the internal sram and flash memory can hold instructions and data. the external bus inte rface has been designed to su pport most of the standard memories used with the mpc5 xx family. the complex input/output timer f unctions of the mpc5500 family are performed by an enhanced time processor unit engine (etpu). the etpu engine c ontrols 32 hardware channels. the etpu has been enhanced over the tpu by providing 24-bit timers, doubl e-action hardware channe ls, variable number of parameters per channel, angle clock hardware, and additional control and arit hmetic instructions. the etpu can be programmed using a high-level programming language. the less complex timer functions of the mpc5500 family are perf ormed by the enhanced modular input/output system (emios). the emios? 24 ha rdware channels are capable of single-action, double-action, pulse-width modulation (pwm), a nd modulus-counter operations. motor control capabilities include edge-ali gned and center-aligned pwm. off-chip communication is performed by a suite of se rial protocols including controller area networks (flexcans), enhanced deserial/seria l peripheral interfaces (dspi), a nd enhanced serial communications interfaces (escis). the dspis suppor t pin reduction through hardware seri alization and deserialization of timer channels and general-purpos e input/output (gpio) signals. the mcu of the mpc5553 has an on-chip 40-channel enhanced queued dual anal og-to-digital converter (eqadc). the system integration unit (siu) performs several chip-wide configuration f unctions. pad configuration and general-purpose input and output (g pio) are controlled from the si u. external interrupts and reset control are also determined by the siu. the internal multiple xer submodule (siu_disr) provides multiplexing of eqadc trigger sources, daisy chai ning the dspis, and external interrupt signal multiplexing. the fast ethernet (fec) module is a risc-based controller that supports both 10 and 100 mbps ethernet/ieee? 802.3 networks and is compatible with three different standard mac (media access controller) phy (physical) in terfaces to connect to an external ethernet bus. the fec supports the 10 or 100 mbps mii (media independent inte rface), and the 10 mbps-only with a seven-wire interface, which uses a subset of the mii signals. the upper 16-bits of the 32-bit ex ternal bus interface (ebi) are used to connect to an external ethernet de vice. the fec contains built-in tran smit and receive message fifos and dma support.
ordering information mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 3 2 ordering information figure 1. mpc5500 family part number example table 1. orderable part numbers freescale part number 1 package description speed (mhz) operating temperature 2 nominal max 3 (f max ) min (t l ) max (t h ) mpc5553mvr132 mpc5553 lead-free 416 package 132 132 ?40 c 125 c mpc5553mvr112 112 114 mpc5553mvr80 80 82 mpc5553mvz132 mpc5553 lead-free 324 package 132 132 ?40 c 125 c mpc5553mvz112 112 114 MPC5553MVZ80 80 82 mpc5553mvm132 mpc5553 lead-free 208 package 132 132 ?40 c 125 c mpc5553mvm112 112 114 mpc5553mvm80 80 82 mpc5553mzp132 mpc5553 lead 416 package 132 132 ?40 c 125 c mpc5553mzp112 112 114 mpc5553mzp80 80 82 mpc5553mzq132 mpc5553 lead 324 package 132 132 ?40 c 125 c mpc5553mzq112 112 114 mpc5553mzq80 80 82 mpc m 80r2 qualification status core code device number temperature range package identifier operating frequency (mhz) tape and reel status temperature range m = ?40 c to 125 c package identifier zp = 416pbga snpb vr = 416pbga pb-free vf = 208mapbga snpb vm = 208mapbga pb-free zq = 324pbga snpb vz = 324pbga pb-free operating frequency 80 = 80 mhz 112 = 112 mhz 132 = 132 mhz tape and reel status r2 = tape and seel (blank) = trays qualification status p = pre qualification m = full spec qualified 5553 zp note: not all options are available on all devices. refer to ta b l e 1 .
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 4 3 electrical characteristics this section contains detailed information on power c onsiderations, dc/ac electric al characteristics, and ac timing specifications for the mcu. 3.1 maximum ratings mpc5553mvf132 mpc5553 lead 208 package 132 132 ?40 c 125 c mpc5553mvf112 112 114 mpc5553mvf80 80 82 1 all devices are ppc5553, rather than mpc555 3, until the product qualifications. not all configurations are available in the ppc parts. 2 the lowest operating temperature is referenced by t l ; the highest operating temperature is referenced by t h . 3 speed is the nominal maximum frequency. max speed is the maximum speed allowed including any frequency modulation. 80 mhz parts allow for 80 mhz + 2% modulation. however, 132 mhz devices allow 128 mhz plus two percent frequency modulation only. table 2. absolute maximum ratings 1 spec characteristic symbol min max 2 unit 1 1.5 v core supply voltage 3 v dd ?0.3 1.7 v 2 flash program/erase voltage v pp ?0.3 6.5 v 3 flash core voltage v ddf ?0.3 1.7 v 4 flash read voltage v flash ?0.3 4.6 v 5 sram standby voltage v stby ?0.3 1.7 v 6 clock synthesizer voltage v ddsyn ?0.3 4.6 v 7 3.3 v i/o buffer voltage v dd33 ?0.3 4.6 v 8 voltage regulator control input voltage v rc33 ?0.3 4.6 v 9 analog supply voltage (reference to v ssa )v dda ?0.3 5.5 v 10 i/o supply voltage (fast i/o pads) 4 v dde ?0.3 4.6 v 11 i/o supply voltage (slow and medium i/o pads) 4 v ddeh ?0.3 6.5 v 12 dc input voltage 5 v ddeh powered i/o pads v dde powered i/o pads v in ?1.0 6 ?1.0 6 6.5 7 4.6 8 v 13 analog reference high voltage (reference to v rl )v rh ?0.3 5.5 v 14 v ss differential voltage v ss ? v ssa ?0.1 0.1 v 15 v dd differential voltage v dd ? v dda ?v dda v dd v 16 v ref differential voltage v rh ? v rl ?0.3 5.5 v table 1. orderable part numbers (continued) freescale part number 1 package description speed (mhz) operating temperature 2 nominal max 3 (f max ) min (t l ) max (t h )
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 5 17 v rh to v dda differential voltage v rh ? v dda ?5.5 5.5 v 18 v rl to v ssa differential voltage v rl ? v ssa ?0.3 0.3 v 19 v ddeh to v dda differential voltage v ddeh ? v dda ?v dda v ddeh v 20 v ddf to v dd differential voltage v ddf ? v dd ?0.3 0.3 v 21 this spec has been moved to ta b l e 9 , spec 43a. 22 v sssyn to v ss differential voltage v sssyn ? v ss ?0.1 0.1 v 23 v rcvss to v ss differential voltage v rcvss ? v ss ?0.1 0.1 v 24 maximum dc digital input current 9 (per pin, applies to all digital pins) 5 i maxd ?2 2 ma 25 maximum dc analog input current 10 (per pin, applies to all analog pins) i maxa ?3 3 ma 26 maximum operating temperature range 11 die junction temperature t j t l 150.0 o c 27 storage temperature range t stg ?55.0 150.0 o c 28 maximum solder temperature 12 t sdr ? 260.0 o c 29 moisture sensitivity level 13 msl ? 3 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stress beyond the listed maxi ma can affect device reliability or caus e permanent damage to the device. 2 absolute maximum voltages are currently maximum burn-in voltage s. absolute maximum specificat ions for device stress have not yet been determined. 3 1.5 v +/? 10% for proper operation. this parameter is specified at a maximum ju nction temperature of 150 o c. 4 all functional non-supply i/o pins are clamped to v ss and v dde , or v ddeh . 5 ac signal overshoot and undershoot of up to +/? 2.0 v of th e input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 6 internal structures hold the voltage greater than ?1.0 v if th e injection current limit of 2 ma is met. keep the negative dc current greater than ?0.6 v on etpub[15] and sinb during the internal power-on reset (por) state. 7 internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specification is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 8 internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specification is met (2 ma for all pins) and v dde is within the operating voltage specifications. 9 total injection current for all pins (including bot h digital and analog) must not exceed 25 ma. 10 total injection current for all analog input pins must not exceed 15 ma. 11 lifetime operation at these specif ication limits is not guaranteed. 12 solder profile per cdf-aec-q100. 13 moisture sensitivity per jedec test method a112. table 2. absolute maximum ratings 1 (continued) spec characteristic symbol min max 2 unit
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 6 3.2 thermal characteristics the shaded rows in the following table indicat e information specific to a four-layer device. 3.2.1 general notes for specifications at maximum junction temperature an estimation of the device junction temperature, t j , can be obtained from the equation: t j = t a + (r ja p d ) where: t a = ambient temperature for the package ( o c) r ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on th e jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference betw een the values determined for the single-layer (1s) board compared to a four-layer boa rd that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal re sistance is not a constant . the thermal resistance depends on the: table 3. thermal characteristics spec mpc5553 thermal characteristic symbol package unit 208 mapbga 324 pbga 416 pbga 1 junction to ambient 1, 2 , natural convection (one-layer board) 1 junction temperature is a function of on-chip power dissi pation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on th e board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 wit h the single-layer board horizontal. r ja 41 30 29 c/w 2 junction to ambient 1, 3 , natural convection (four-layer board 2s2p) 3 per jedec jesd51-6 with the board horizontal. r ja 25 21 21 c/w 3 junction to ambient (@200 ft./min., one-layer board) r jma 33 24 23 c/w 4 junction to ambient (@200 ft./min., four-layer board 2s2p) r jma 22 17 18 c/w 5 junction to board 4 (four-layer board 2s2p) 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 15 12 13 c/w 6 junction to case 5 5 indicates the average thermal resistance between the die and th e case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. r jc 789c/w 7 junction to package top 6 , natural convection 6 thermal characterization parameter indicating the temperatur e difference between package top and the junction temperature per jedec jesd51-2. jt 222c/w
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 7 ? construction of the applicati on board (number of planes) ? effective size of the board which cools the component ? quality of the thermal and elec trical connections to the planes ? power dissipated by adjacent components connect all the ground and powe r balls to the resp ective planes with one via pe r ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias le ave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtaine d on a single-layer board is within the normal range for the tightly packed printed circuit board. the valu e obtained on a board with the intern al planes is usually within the normal range if the application board has: ? one oz (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depe nds on the power dissipation of the surrounding components. in addition, th e ambient temperature varies widely wi thin the application. for many natural convection and especially closed box applications, the board temperatur e at the perimeter (edge) of the package is approximately the same as the local ai r temperature near the device. specifying the local ambient conditions explicitly as the board temperatur e provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t b + (r jb p d ) where: t j = junction temperature ( o c) t b = board temperature at the package perimeter ( o c/w) r jb = junction-to-board thermal resistance ( o c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor into the cal culation, an acceptable value for the junction temperature is predictable. ensure th e application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junction-to-case th ermal resistance plus a case-to-ambient th ermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( o c/w) r jc = junction-to-case thermal resistance ( o c/w) r ca = case-to-ambient thermal resistance ( o c/w)
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 8 r jc is device related and is not affected by other fact ors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ca . for example, change the air flow around the device, add a heat sink, change the mount ing arrangement on printed circui t board, or change the thermal dissipation on the printed circuit board surrounding th e device. this descripti on is most useful for packages with heat sinks where 90% of the heat flow is through th e case to the heat si nk to ambient. for most packages, a better model is required. a more accurate two-resistor th ermal model can be constructed fr om the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case ther mal resistance describes when using a heat sink or where a s ubstantial amount of heat is dissipat ed from the top of the package. the junction-to-board thermal resistan ce describes the thermal performanc e when most of the heat is conducted to the printed circuit board. this model can be used to generate si mple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the devi ce in the application on a prototype board, use the thermal characterization parameter ( jt ) to determine the junction temperature by measuring the temperature at the top center of the p ackage case using the following equation: t j = t t + ( jt p d ) where: t t = thermocouple temperature on top of the package ( o c) jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compliance with the je sd51-2 specific ation using a 40-gauge type t thermoc ouple epoxied to the top center of the package case. position the thermocouple so that the thermocouple juncti on rests on the package. a small amount of epoxy is placed on the thermocouple junction and approximately 1 mm of wi re extending from the junction. the thermocouple wire is placed flat against the package case to avoi d measurement errors caused by the cooling effects of the thermocouple wire. references: semiconductor equipment and materials inte rnational 805 east middlefield rd. mountain view, ca., 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) spec ifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . ? 1. c.e. triplett and b. joiner, ?an experime ntal characterization of a 272 pbga within an automotive engine controller module,? pr oceedings of semitherm, san diego, 1998, pp. 47?54. ? 2. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electr onic packaging and production, pp. 53?58, march 1998. ? 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedi ngs of semitherm, san diego, 1999, pp. 212?220.
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 9 3.3 package the mpc5553 is available in packaged form. package options are listed in section 2, ?ordering information .? refer to section 4, ?mechanicals,? for pinouts and package drawings. 3.4 emi (electromagnetic interference) characteristics 3.5 esd characteristics table 4. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 19 95-03. qualification testing was performed on the mpc5554 and applied to the mpc5500 family as generic emi performance data. spec characteristic minimum typical maximum unit 1 scan range 0.15 ? 1000 mhz 2 operating frequency ? ? 132 mhz 3v dd operating voltages ? 1.5 ? v 4v ddsyn , v rc33 , v dd33 , v flash , v dde operating voltages ? 3.3 ? v 5v pp , v ddeh , v dda operating voltages ? 5.0 ? v 6 maximum amplitude ? ? 14 2 32 3 2 measured with single-chip emi program. 3 measured with expanded emi program. dbuv 7 operating temperature ? ? 25 o c table 5. esd ratings 1, 2 1 all esd testing conforms to cdf-aec -q100 stress test qualification for automotive grade integrated circuits. 2 device failure is defined as: if after exposure to esd pulses, t he device no longer meets the device specification requirements . complete dc parametric and functional testing will be perform ed per applicable device specification at room temperature followed by hot temperature, unless specif ied otherwise in the device specification. characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 c100 pf esd for field induced charge model (fdcm) 500 (all pins) v 750 (corner pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 10 3.6 voltage regulator controller (v rc ) and power-on reset (por) electrical specifications table 6. vrc/por electr ical specifications spec characteristic symbol min max units 1 1.5 v (v dd ) por negated (ramp up) 1.5 v (v dd ) por asserted (ramp down) v_por15 1.1 1.1 1.35 1.35 v 2 3.3 v (v ddsyn ) por negated (ramp up) 3.3 v (v ddsyn ) por asserted (ramp down) v_por33 2.0 2.0 2.85 2.85 v 3 reset pin supply (v ddeh6 ) por negated (ramp up) 1 reset pin supply (v ddeh6 ) por asserted (ramp down) 1 1 v il_s ( ta b l e 9 , spec15) is guaranteed to scale with v ddeh6 down to v_por5. v_por5 2.0 2.0 2.85 2.85 v 4v rc33 voltage before the regulator controller allows the pass transistor to start turning on v_trans_start 1.0 2.0 v 5v rc33 voltage when the regulator controller allows the pass transistor to completely turn on 2, 3 2 supply full operating current for the 1.5 v su pply when the 3.3 v supply reaches this range. 3 it is possible to reach the current limit during ramp up?do not treat this event as short circuit current. v_trans_on 2.0 2.85 v 6v rc33 voltage greater than t he voltage at which the v rc keeps the 1.5 v supply in regulation 4, 5 4 at peak current for device. 5 requires compliance with freescale?s recommended board r equirements and transistor recommendations. board signal traces/routing from the v rcctl package signal to the base of the external pass transistor and between the emitter of the pass transistor to the v dd package signals must have a maximum of 100 nh inductance and minimal resistance (less than 1 ). v rcctl must have a nominal 1 f phase compensation capacitor to ground. v dd must have a 20 f (nominal) bulk capacitor (greater than 4 f over all conditions, including lifetime). place high-frequency bypass capacitors consisting of eight 0.01 f, two 0.1 f, and one 1 f capacitors around the package on the v dd supply signals. v_v rc33reg 3.0 ? v 7 current can be sourced by v rcctl i_v rcctl 6 6 i_vrcctl is measured at the following conditions: v dd = 1.35 v, v rc33 = 3.1 v, v_vrcctl = 2.2 v. ma ? 40 o c 11.0 ? ma 25 o c 9.0 ? ma 150 o c (tj) 7.5 ? ma 8 voltage differential during power up such that: v dd33 can lag v ddsyn or v ddeh6 , before v ddsyn and v ddeh6 reach the v_por33 and v_por5 minimums respectively. v dd33 _lag ? 1.0 v 9 absolute value of slew rate on power supply pins ? 50 v/ms 10 required gain: i dd / i_v rcctl (@v dd = 1.35 v, f sys = f max ) 5 , 7 7 values are based on idd from high-use applications as explained in the idd electrical specification. beta 8 8 beta is measured on a per-part basis and is calculated as (idd i_vrcctl), and represents the worst-case external transistor beta. ? 40 o c 55.0 9 ?? 25 o c 58.0 9 ?? 150 o c (tj) 70.0 9 500 ?
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 11 3.7 power-up/down sequencing power sequencing between th e 1.5 v power supply and v ddsyn or the reset power supplies is required if using an external 1.5 v power supply with v rc33 tied to ground (gnd). to avoid power-sequencing, v rc33 must be powered up within the specified operati ng range, even if the on-chip voltage regulator controller is nit used. refer to section 3.7.2, ?power-up sequence (vrc33 grounded) , ? and section 3.7.3, ?power-down sequence (vrc33 grounded) . ? power sequencing requires that v dd33 must reach a certain voltage where the values are read as ones before the por signal negates. refer to section 3.7.1, ?input value of pins during por dependent on vdd33 . ? although power sequencing is not required between v rc33 and v ddsyn during power up, v rc33 must not lead v ddsyn by more than 600 mv or lag by more than 100 mv for the v rc stage turn-on to operate within specification. higher spikes in the emitte r current of the pass transistor occur if v rc33 leads or lags v ddsyn by more than these amounts. the value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. furthermore, when all of the pors negate, the system clock starts to toggle, adding another large increase of the current consumed by v rc33 . if v rc33 lags v ddsyn by more than 100 mv, the increase in current consumed can drop v dd low enough to assert the 1.5 v por agai n. oscillations are possible when the 1.5 v por asserts and stops the syst em clock, causing the voltage on v dd to rise until the 1.5 v por negates again. all osci llations stop when v rc33 is powered sufficiently. when powering down, v rc33 and v ddsyn have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. wh en not powering up or down, no delta between v rc33 and v ddsyn is required for the v rc to operate within specification. there are no power up/down sequencing requirements to prevent issues su ch as latch-up, excessive current spikes, and so on. therefore, the state of the i/o pins during powe r up/down varies depending on which supplies are powered. table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type). 9 preliminary value. final specification pending characterization. table 7. power sequence pin status for fast pads v dde v dd33 v dd por pin status for fast pad output driver pad_fc (fast) low ? ? asserted low v dde low low asserted high v dde low v dd asserted high v dde v dd33 low asserted high impedance (hi-z) v dde v dd33 v dd asserted hi-z v dde v dd33 v dd negated functional
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 12 table 8 gives the pin state for the sequence cases for a ll pins with pad type pad_mh (medium type) and pad_sh (slow type). 3.7.1 input value of pins during por dependent on v dd33 when powering up the device, v dd33 must not lag the latest v ddsyn or reset power pin (v ddeh6 ) by more than the v dd33 lag specification listed in table 6 , spec 8. this avoids accidentally selecting the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are not powered and therefore cannot read the defaul t state when por negates. v dd33 can lag v ddsyn or the reset power pin (v ddeh6 ), but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification applies during power up only. v dd33 has no lead or lag requirements when powering down. 3.7.2 power-up sequence (v rc33 grounded) the 1.5 v v dd power supply must rise to 1.35 v before the 3.3 v v ddsyn power supply and the r eset power supply rises above 2.0 v. this ensures that digital logic in th e pll for the 1.5 v power supply does not begin to operate below the spec ified operation range lower limit of 1.35 v. because the internal 1.5 v por is disabled, the internal 3.3 v por or the reset power por must hold th e device in reset. since they can negate as low as 2.0 v, v dd must be within specification be fore the 3.3 v por and the reset por negate. figure 2. power-up sequence (v rc33 grounded) table 8. power sequence pin status for medium / slow pads v ddeh v dd por pin status for medium and slow pad output driver pad_mh (medium) pad_sh (slow) low ? asserted low v ddeh low asserted high impedance (hi-z) v ddeh v dd asserted hi-z v ddeh v dd negated functional v ddsyn and reset power v dd 2.0 v 1.35 v v dd must reach 1.35 v before v ddsyn and the reset power reach 2.0 v
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 13 3.7.3 power-down sequence (v rc33 grounded) the only requirement for the power-down sequence when v rc33 is grounded is that if v dd decreases to less than its operating range, v ddsyn or the reset power must decrease to less than 2.0 v before the v dd power is allowed to increase to its operating range. this ensures that the digital 1.5 v logic, which is reset by the ored por only and can cause the 1.5 v suppl y to decrease below its specification, is reset properly. 3.8 dc electrical specifications table 9. dc electrical specifications spec characteristic symbol min max unit 1 core supply voltage (average dc rms voltage) v dd 1.35 1.65 v 2 i/o supply voltage (fast i/o) v dde 1.62 3.6 v 3 i/o supply voltage (slow / medium i/o) v ddeh 3.0 5.25 v 4 3.3 v i/o buffer voltage v dd33 3.0 3.6 v 5 voltage regulator control input voltage v rc33 3.0 3.6 v 6 analog supply voltage 1 v dda 4.5 5.25 v 8 flash programming voltage 2 v pp 4.5 5.25 v 9 flash read voltage v flash 3.0 3.6 v 10 sram standby voltage 3 v stby 0.8 1.2 v 11 clock synthesizer operating voltage v ddsyn 3.0 3.6 v 12 fast i/o input high voltage v ih_f 0.65 v dde v dde + 0.3 v 13 fast i/o input low voltage v il_f v ss ? 0.3 0.35 v dde v 14 medium / slow i/o input high voltage v ih_s 0.65 v ddeh v ddeh + 0.3 v 15 medium / slow i/o input low voltage v il_s v ss ? 0.3 0.35 v ddeh v 16 fast i/o input hysteresis v hys_f 0.1 v dde v 17 medium / slow i/o input hysteresis v hys_s 0.1 v ddeh v 18 analog input voltage v indc v ssa ? 0.3 v dda + 0.3 v 19 fast i/o output high voltage ( i oh_f = ?2.0 ma ) v oh_f 0.8 v dde ?v 20 slow / medium i/o output high voltage ( i oh_s = ?2.0 ma ) v oh_s 0.8 v ddeh ?v 21 fast i/o output low voltage ( i ol_f = 2.0 ma ) v ol_f ?0.2 v dde v 22 slow / medium i/o output low voltage ( i ol_s = 2.0 ma ) v ol_s ?0.2 v ddeh v 23 load capacitance (fast i/o) 4 dsc (siu_pcr[8:9] ) = 0b00 dsc (siu_pcr[8:9] ) = 0b01 dsc (siu_pcr[8:9] ) = 0b10 dsc (siu_pcr[8:9] ) = 0b11 c l ? ? ? ? 10 20 30 50 pf pf pf pf
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 14 24 input capacitance (digital pins) c in ?7pf 25 input capacitance (analog pins) c in_a ?10pf 26 input capacitance (shared digital and analog pins an[12]_ma[0]_sds , an[12]_ma[1]_sdo, an[14]_m a[2]_sdi, and an[15]_fck) c in_m ?12pf 27a operating current 5 1.5 v supplies @ 132 mhz: v dd (including v ddf max current) 6, 7 @1.65 v typical use v dd (including v ddf max current) 6 , 7 @1.35 v typical use v dd (including v ddf max current) 7 , 8 @1.65 v high use v dd (including v ddf max current) 7 , 8 @1.35 v high use idd idd idd idd ? ? ? ? 550 9 450 9 600 9 490 9 ma ma ma ma 27b operating current 5 1.5 v supplies @ 114 mhz: v dd (including v ddf max current) 6 , 7 @1.65 v typical use v dd (including v ddf max current) 6 , 7 @1.35 v typical use v dd (including v ddf max current) 7 , 8 @1.65 v high use v dd (including v ddf max current) 7 , 8 @1.35 v high use idd idd idd idd ? ? ? ? 460 9 380 9 520 9 420 9 ma ma ma ma 27c operating current 5 1.5 v supplies @ 82 mhz: v dd (including v ddf max current) 6 , 7 @1.65 v typical use v dd (including v ddf max current) 6 , 7 @1.35 v typical use v dd (including v ddf max current) 7 , 8 @1.65 v high use v dd (including v ddf max current) 7 , 8 @1.35 v high use idd idd idd idd ? ? ? ? 350 9 290 9 400 9 330 9 ma ma ma ma 27d refer to figure 3 for an interpolation of this data. 10 idd stby @ 25 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v idd stby @ 60 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v idd stby @ 150 o c (tj) v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v idd stby idd stby idd stby idd stby idd stby idd stby idd stby idd stby idd stby ? ? ? ? ? ? ? ? ? 20 30 50 70 100 200 1200 1500 2000 a a a a a a a a a 28 operating current 3.3 v supplies @ 132 mhz v dd33 11 idd 33 ?2 + (values derived from procedure of footnote 11 ) ma v flash i vflash ?10ma v ddsyn i ddsyn ?15ma table 9. dc electrical specifications (continued) spec characteristic symbol min max unit
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 15 29 operating current 5.0 v supplies (12 mhz adclk): v dda (v dda0 + v dda1 ) analog reference supply current (v rh , v rl ) v pp idd a i ref i pp ? ? ? 20.0 1.0 25.0 ma ma ma 30 operating current v dde 12 supplies: v ddeh1 v dde2 v dde3 v ddeh4 v dde5 v ddeh6 v dde7 v ddeh8 v ddeh9 idd1 idd2 idd3 idd4 idd5 idd6 idd7 idd8 idd9 ? ? ? ? ? ? ? ? ? refer to footnote 12 ma ma ma ma ma ma ma ma ma 31 fast i/o weak pullup current 13 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v i act_f 10 20 20 110 130 170 a a a fast i/o weak pulldown current 13 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v 10 20 20 100 130 170 a a a 32 slow / medium i/o weak pullup/down current 14 3.0?3.6 v 4.5?5.5 v i act_s 10 20 150 170 a a 33 i/o input leakage current 15 i inact_d ? 2.5 2.5 a 34 dc injection current (per pin) i ic ? 2.0 2.0 ma 35 analog input current, channel off 16 i inact_a ?150 150 na 35a analog input current, shared analog / digital pins (an[12], an[13], an[14], an[15]) i inact_ad ? 2.5 2.5 a 36 v ss differential voltage 17 v ss ? v ssa ? 100 100 mv 37 analog reference low voltage v rl v ssa ? 0.1 v ssa + 0.1 v 38 v rl differential voltage v rl ? v ssa ?100 100 mv 39 analog reference high voltage v rh v dda ? 0.1 v dda + 0.1 v 40 v ref differential voltage v rh ? v rl 4.5 5.25 v 41 v sssyn to v ss differential voltage v sssyn ? v ss ?50 50 mv 42 v rcvss to v ss differential voltage v rcvss ? v ss ?50 50 mv 43 v ddf to v dd differential voltage 2 v ddf ? v dd ?100 100 mv 43a v rc33 to v ddsyn differential voltage v rc33 ? v ddsyn ?0.1 0.1 18 v table 9. dc electrical specifications (continued) spec characteristic symbol min max unit
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 16 44 analog input differential signal range (with common mode 2.5 v) v idiff ? 2.5 2.5 v 45 operating temperature range, ambient (packaged) t a = (t l to t h )t l t h c 46 slew rate on power-supply pins ? ? 50 v/ms 1 | v dda0 ? v dda1 | must be < 0.1 v. 2 v pp can drop to 3.0 v during read operations. 3 during standby operation, if standby operation is not required, connect v stby to ground. 4 applies to clkout, external bus pins, and nexus pins. 5 maximum average rms dc current. 6 average current measured on automotive benchmark. 7 peak currents can be higher on specialized code. 8 high use current measured while running optimized spe asse mbly code with all code and data 100% locked in cache (0% miss rate) with all channels of the emios and etpu running autonomously, plus the edma tr ansferring data continuously from sram to sram. higher currents are possible if an idle loop that crosses cache lines is run from cache. design and write code to avoid this condition. 9 preliminary. final specification pending characterization. 10 figure 3 shows an illustration of the idd stby values interpolated for these temperature values. 11 power requirements for the v dd33 supply depend on the frequency of operation and load of all i/o pins, and the voltages on the i/o segments. refer to ta bl e 1 1 for values to calculate power dissipation for specific operation. 12 power requirements for each i/o segment are dependent on the fr equency of operation and load of the i/o pins on a particular i/o segment, and the voltage of the i/o segment. refer to ta bl e 1 0 for values to calculate power dissipation for specific operation. the total power consumption of an i/o segment is th e sum of the individual power co nsumptions for each pin on the segment. 13 absolute value of current, measured at v il and v ih . 14 absolute value of current, measured at v il and v ih . 15 weak pullup/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types: pad_fc, pad_sh, and pad_mh. 16 maximum leakage occurs at maximum operating temperature. leakage current decreases by approximately one-half for each 8 o c to 12 o c, in the ambient temperature range of 50 o c to 125 o c. applies to pad types: pad_a and pad_ae. 17 v ssa refers to both v ssa0 and v ssa1 . | v ssa0 ? v ssa1 | must be < 0.1 v. 18 up to 0.6 v during power up and power down. table 9. dc electrical specifications (continued) spec characteristic symbol min max unit
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 17 figure 3 shows an approximate interpolation of the i stby worst-case specification to help estimate the values at different voltages and temperatures. the vertical lines inside the graph show the actual specifications listed in table 9 . refer to the idd stby specifications (27d) in table 9 for more information. figure 3. i stby worst-case specifications 3.8.1 i/o pad current specifications the power consumption of an i/o se gment depends on the usage of the pi ns on a particular segment. the power consumption is the sum of al l output pin currents for a particul ar segment. the output pin current can be calculated from table 10 based on the voltage, frequency, and lo ad on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 10 . 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0.8v 1.0v 1.2v a i stby related to junction temperature temperature (c)
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 18 table 10. i/o pad average dc current 1 1 these values are estimates from simulation and ar e not tested. currents apply to output pins only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. voltag e (v) drive select / slew rate control setting current (ma) 1 slow idrv_sh 25 50 5.25 11 8.0 210505.25013.2 3 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 5 medium idrv_mh 50 50 5.25 11 17.3 620505.25016.5 7 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9 9 fast idrv_fc 66 10 3.6 00 2.8 10 66 20 3.6 01 5.2 11 66 30 3.6 10 8.5 12 66 50 3.6 11 11.0 13 66 10 1.98 00 1.6 14 66 20 1.98 01 2.9 15 66 30 1.98 10 4.2 16 66 50 1.98 11 6.7 17 56 10 3.6 00 2.4 18 56 20 3.6 01 4.4 19 56 30 3.6 10 7.2 20 56 50 3.6 11 9.3 21 56 10 1.98 00 1.3 22 56 20 1.98 01 2.5 23 56 30 1.98 10 3.5 24 56 50 1.98 11 5.7 25 40 10 3.6 00 1.7 26 40 20 3.6 01 3.1 27 40 30 3.6 10 5.1 28 40 50 3.6 11 6.6 29 40 10 1.98 00 1.0 30 40 20 1.98 01 1.8 31 40 30 1.98 10 2.5 32 40 50 1.98 11 4.0
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 19 3.8.2 i/o pad v dd33 current specifications the power consumption of the v dd33 supply dependents on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v dd33 currents for all i/ o segments. the output pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. the input pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all pad_sh and pad_sh pins. use li near scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 11 . table 11. v dd33 pad average dc current 1 1 these values are estimated from simulation and not tested. currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. v dd33 (v) v dde (v) drive select current (ma) inputs 1 slow i33_sh 66 0.5 3.6 5.5 na 0.003 2 medium i33_mh 66 0.5 3.6 5.5 na 0.003 outputs 3 fast i33_fc 66 10 3.6 3.6 00 0.35 466203.63.6010.53 566303.63.6100.62 666503.63.6110.79 7 66 10 3.6 1.98 00 0.35 8 66 20 3.6 1.98 01 0.44 9 66 30 3.6 1.98 10 0.53 10 66 50 3.6 1.98 11 0.7 11 56 10 3.6 3.6 00 0.30 12 56 20 3.6 3.6 01 0.45 13 56 30 3.6 3.6 10 0.52 14 56 50 3.6 3.6 11 0.67 15 56 10 3.6 1.98 00 0.30 16 56 20 3.6 1.98 01 0.37 17 56 30 3.6 1.98 10 0.45 18 56 50 3.6 1.98 11 0.60 19 40 10 3.6 3.6 00 0.21 20 40 20 3.6 3.6 01 0.31 21 40 30 3.6 3.6 10 0.37 22 40 50 3.6 3.6 11 0.48 23 40 10 3.6 1.98 00 0.21 24 40 20 3.6 1.98 01 0.27 25 40 30 3.6 1.98 10 0.32 26 40 50 3.6 1.98 11 0.42
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 20 3.9 oscillator and fmpll electrical characteristics table 12. fmpll electrical specifications (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symbol minimum maximum unit 1 pll reference frequency range: crystal reference external reference dual controller (1:1 mode) f ref_crystal f ref_ext f ref_1:1 8 8 24 20 20 f sys 2 mhz 2 system frequency 1 f sys f ico ( min ) 2 rfd f max 2 mhz 3 system clock period t cyc ?1 f sys ns 4 loss of reference frequency 3 f lor 100 1000 khz 5 self clocked mode (scm) frequency 4 f scm 7.4 17.5 mhz 6 extal input high voltage crystal mode 5 all other modes (dual controller (1:1), bypass, external reference) v ihext v ihext v xtal + 0.4 v [(v dde5 2) + 0.4 v] ? ? v v 7 extal input low voltage crystal mode 6 all other modes (dual controller (1:1), bypass, external reference) v ilext v ilext ? ? v xtal ? 0.4 v [(v dde5 2) ? 0.4 v] v v 8 xtal current 7 i xtal 0.8 3 ma 9 total on-chip stray capacitance on xtal c s_xtal ?1.5pf 10 total on-chip stray capacitance on extal c s_extal ?1.5pf 11 crystal manufacturer?s recommended capacitive load c l refer to crystal specification refer to crystal specification pf 12 discrete load capacitance to connect to extal c l_extal ?(2 c l ) ? c s_extal ? c pcb_extal 8 pf 13 discrete load capacitance to connect to xtal c l_xtal ?(2 c l ) ? c s_xtal ? c pcb_xtal 8 pf 14 pll lock time 9 t lpll ?750 s 15 dual controller (1:1) clock skew (between clkout and extal) 10, 11 t skew ?2 2 ns 16 duty cycle of reference t dc 40 60 % 17 frequency un-lock range f ul ? 4.0 4.0 % f sys 18 frequency lock range f lck ? 2.0 2.0 % f sys
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 21 19 clkout period jitter, 12, 13 measured at f sys maximum peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5.0 0.01 % f clkout 20 frequency modulation range limit 14 (do not exceed f sys maximum) c mod 0.8 2.4 %f sys 21 ico frequency f ico = [ f ref (mfd + 4) ] (prediv + 1) 15 f ico 48 f sys mhz 22 predivider output frequency (to pll) f prediv 4f max mhz 1 all internal registers retain data at 0 hz. 2 up to the maximum frequency rati ng of the device (refer to ta b l e 1 ). 3 loss of reference frequency is defined as the reference freque ncy detected internally, which transitions the pll into self-clocked mode. 4 the pll operates at self-clocked mode (scm) frequency when the reference frequency falls below f lor . scm frequency is measured on the clkout ball with the divider set to divide-by-two of the system clock. note: in scm, the mfd and prediv have no effect and the rfd is bypassed. 5 use the extal input high voltage parameter when using the fl excan oscillator in crystal mode (no quartz crystals or resonators). (v extal ? v xtal ) must be 400 mv for the oscillator?s comparator to produce the output clock. 6 use the extal input low voltage parameter when using the flexcan oscillator in crystal mode (no quartz crystals or resonators). (v xtal ?v extal ) must be 400 mv for the oscillator?s comparator to produce the output clock. 7 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. 8 c pcb_extal and c pcb_xtal are the measured pcb stray capacitan ces on extal and xtal, respectively. 9 this specification applies to the period r equired for the pll to relock after changi ng the mfd frequency control bits in the synthesizer control register (syncr). from power up with crystal oscillator reference, the lock time also includes the crystal startup time. 10 pll is operating in 1:1 pll mode. 11 v dde = 3.0?3.6 v 12 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the jitter percentage for a given interval. clkout divider is set to divide-by-two. 13 values are with frequency modulation disabled. if frequency m odulation is enabled, jitter is the sum of (jitter + cmod). 14 modulation depth selected must not result in f sys value greater than the f sys maximum specified value. 15 f sys = f ico (2 rfd ). table 12. fmpll electrical specifications (continued) (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symbol minimum maximum unit
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 22 3.10 eqadc electrical characteristics table 13. eqadc conversion specifications (operating) spec characteristic symbol minimum maximum unit 1 adc clock (adclk) frequency 1 1 conversion characteristics vary with f adclk rate. reduced conversion accuracy occurs at maximum f adclk rate. the maximum value is based on 800 ks/s and the minimum value is based on 20 mhz oscillator clock frequency divided by a maximum 16 factor. f adclk 112mhz 2 conversion cycles differential single ended cc 13 + 2 (15) 14 + 2 (16) 13 + 128 (141) 14 + 128 (142) adclk cycles 3 stop mode recovery time 2 2 stop mode recovery time begins when the adc control register enable bits are set until the adc is ready to perform conversions. t sr 10 ? s 4 resolution 3 3 at v rh ? v rl = 5.12 v, one least significant bit (lsb) = 1.25, mv = one count. ?1.25 ? mv 5 inl: 6 mhz adc clock inl6 ?4 4 counts 3 6 inl: 12 mhz adc clock inl12 ?8 8 counts 7 dnl: 6 mhz adc clock dnl6 ?3 4 4 guaranteed 10-bit monotonicity. 3 4 counts 8 dnl: 12 mhz adc clock dnl12 ?6 4 6 4 counts 9 offset error with calibration offwc ?4 5 5 the absolute value of the offset error without calibration 100 counts. 4 5 counts 10 full-scale gain error with calibration gainwc ?8 6 6 the absolute value of the full scale gain error without calibration 120 counts. 8 6 counts 11 disruptive input injection current 7, 8, 9, 10 7 below disruptive current conditions, the channel being stressed has conversion values of: 0x3ff for analog inputs greater than v rh , and 0x000 for values less than v rl . this assumes that v rh v dda and v rl v ssa due to the presence of the sample amplifier. other channels are not af fected by non-disruptive conditions. 8 exceeding the limit can cause a conversion error on both stressed and unstressed channels. transi tions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 10 condition applies to two adjacent pads on the internal pad. i inj ?1 1 ma 12 incremental error due to inject ion current. all channels have same 10 k < rs <100 k channel under test has rs = 10 k , i inj = i injmax , i injmin e inj ?4 4 counts 13 total unadjusted error for single ended conversions with calibration 11, 12, 13, 14, 15 11 the tue specification is always less t han the sum of the inl, dn l, offset, and gain errors due to canceling errors. 12 tue does not apply to differential conversions. 13 measured at 6 mhz adc clock. tue with a 12 mhz adc clock is: ?16 counts < tue < 16 counts. 14 tue includes all internal device errors such as internal reference variation (75% ref, 25% ref). 15 depending on the input impedance, the analog input leakage curr ent (dc electrical specification 35a) can affect the actual tue measured on analog channels an[12], an[13], an[14], an[15]. tue ?4 4 counts
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 23 3.11 h7fa flash memory electrical characteristics spec table 14. flash program and erase specifications 1 1 typical program and erase times assume nominal supply values and operation at 25 o c. spec flash program characteristic symbol min typical initial max 2 2 initial factory condition: 100 program/erase cycles, 25 o c, typical supply voltage, 80 mhz minimum system frequency. max 3 3 the maximum erase time occurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. unit 3 doubleword (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. t dwprogram ?10?500 s 4 page program time 4 t pprogram ?2244 5 5 page size is 256 bits (8 words). 500 s 7 16 kbyte block pre-program and erase time t 16kpperase ? 325 525 5000 ms 9 48 kbyte block pre-program and erase time t 48kpperase ? 435 525 5000 ms 10 64 kbyte block pre-program and erase time t 64kpperase ? 525 675 5000 ms 8 128 kbyte block pre-program and erase time t 128kpperase ? 675 1800 15,000 ms 11 minimum operating frequency for program and erase operations 6 6 read frequency of the flash can be up to the maximum operating frequency of the device. there is no minimum read frequency condition. ?25???mhz table 15. flash eeprom module life (full temperature range) spec characteristic symbol min typical 1 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typical endurance, refer to engineering bulletin eb619 typical endurance for nonvolatile memory . unit 1a number of program/erase cycles per block for 16 kbyte, 48 kbyte, and 64 kbyte blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 1b number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) p/e 10,000 100,000 cycles 2 data retention blocks with 0?1,000 p/e cycles blocks with 1,001?100,000 p/e cycles retention 20 5 ?years
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 24 table 16 shows the flash_biu settings versus frequency of operation. refer to the device reference manual for definitions of these bit fields. 3.12 ac specifications 3.12.1 pad ac specifications table 16. flash_biu settings vs. frequency of operation maximum frequency (mhz) apc rwsc wwsc dpfen ipfen pflim bfen up to and including 82 mhz 1 1 allows for 80 mhz system clock with 2% frequency modulation. 0b001 0b001 0b01 0b00, 0b01, or 0b11 2 2 for maximum flash performance, set to 0b11. 0b00, 0b01, or 0b11 2 0b000 to 0b110 3 3 for maximum flash performance, set to 0b110. 0b0, 0b1 4 4 for maximum flash performance, set to 0b1. up to and including 102 mhz 5 5 allows for 100 mhz system clock with 2% frequency modulation. 0b001 0b010 0b01 0b00, 0b01, or 0b11 2 0b00, 0b01, or 0b11 2 0b000 to 0b110 3 0b0, 0b1 4 up to and including132 mhz 6 6 allows for 128 mhz system clock with 2% frequency modulation. 0b010 0b011 0b01 0b00, 0b01, or 0b11 2 0b00, 0b01, or 0b11 2 0b000 to 0b110 3 0b0, 0b1 4 default setting after reset 0b111 0b111 0b11 0b00 0b00 0b000 0b0 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 spec pad src/dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 26 15 50 82 60 200 01 75 40 50 137 80 200 00 377 200 50 476 260 200 2 medium high voltage (mh) 11 16 8 50 43 30 200 01 34 15 50 61 35 200 00 192 100 50 239 125 200
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 25 3fast 00 3.1 2.7 10 01 2.5 20 10 2.4 30 11 2.3 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9000 50 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at f sys = 132 mhz, v dd = 1.35?1.65 v, v dde = 1.62?1.98 v, v ddeh = 4.5?5.5 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h . 2 this parameter is supplied for reference and is guaranteed by design and tested. 3 out delay is shown in figure 4 . add a maximum of one system clock to the ou tput delay for delay with respect to system clock. 4 delay and rise and fall are measured to 20% or 80% of the respective signal. 5 this parameter is guaranteed by characterizati on before qualification ra ther than 100% tested. table 18. de-rated pad ac specifications (v ddeh = 3.3 v, v dde = 3.3 v) 1 1 these are worst-case values that are es timated from simulation and not tested. th e values in the table are simulated at: f sys = 132 mhz; v dd = 1.35?1.65 v; v dde = 3.0?3.6 v; v ddeh = 3.0?3.6 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a = t l to t h . spec pad src/dsc (binary) out delay 2, 3, 4 (ns) rise/fall 3 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 39 23 50 120 87 200 01 101 52 50 188 111 200 00 507 248 50 597 312 200 2 medium high voltage (mh) 11 23 12 50 64 44 200 01 50 22 50 90 50 200 00 261 123 50 305 156 200 3fast 00 3.2 2.4 10 01 2.2 20 10 2.1 30 11 2.1 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9500 50 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 (continued) spec pad src/dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf)
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 26 figure 4. pad output delay 3.13 ac timing 3.13.1 reset and configuration pin timing 2 this parameter is supplied for reference and is guaranteed by design and tested. 3 the delay, and the rise and fall, are measured to 20% or 80% of the respective signal. 4 out delay is shown in figure 4 . add a maximum of one system clock to the output delay for delay with respect to system clock. 5 this parameter is guaranteed by characterization before qualification rather than 100% tested. table 19. reset and configuration pin timing 1 1 reset timing specified at: f sys = 132 mhz; v ddeh = 3.0?5.25 v; v dd = 1.35?1.65 v; and t a = t l to t h . spec characteristic symbol min max unit 1 reset pulse width t rpw 10 ? t cyc 2 reset glitch detect pulse width t gpw 2?t cyc 3 pllcfg, bootcfg, wkpcfg, rstcfg setup time to rstout valid t rcsu 10 ? t cyc 4 pllcfg, bootcfg, wkpcfg, rstcfg hold time from rstout valid t rch 0?t cyc v dd 2 v oh v ol rising-edge out delay falling-edge pad internal data pad output out delay input signal
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 27 figure 5. reset and configuration pin timing 3.13.2 ieee 1149.1 interface timing table 20. jtag pin ac electrical characteristics 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at v dd = 1.35?1.65 v, v dde = 3.0?3.6 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 30 pf with dsc = 0b10, src = 0b11. refer to ta b l e 2 1 for functional specifications. spec characteristic symbol min max unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde 2) t jdc 40 60 ns 3 tck rise and fall times (40% to 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?20ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling-edge to output valid t bsdv ?50ns 12 tck falling-edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling-edge to output high impedance (hi-z) t bsdhz ?50ns 14 boundary scan input valid to tck rising-edge t bsdst 50 ? ns 15 tck rising-edge to boundary scan input invalid t bsdht 50 ? ns 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg rstcfg
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 28 figure 6. jtag test clock input timing figure 7. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 29 figure 8. jtag jcomp timing tck jcomp 9 10
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 30 figure 9. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 31 3.13.3 nexus timing figure 10. nexus output timing table 21. nexus debug port timing 1 1 jtag specifications apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.35?1.65 v, v dde = 2.25?3.6 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 30 pf with dsc = 0b10. spec characteristic symbol min max unit 1 mcko cycle time t mcyc 1 2 2 the nexus aux port runs up to 82 mhz. set npc_pcr[mcko_div] to di vide-by-two if the system frequency is greater than 82 mhz. 8t cyc 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until the next mcko low cycle occurs. t mdov ?1.5 3.0 ns 4 mcko low to mseo data valid 3 t mseov ?1.5 3.0 ns 5 mcko low to evto data valid 3 t evtov ?1.5 3.0 ns 6 evti pulse width t evtipw 4.0 ? t tcyc 7 evto pulse width t evtopw 1?t mcyc 8 tck cycle time t tcyc 4 4 4 limit the maximum frequency to approximately 16 mhz (v dde = 2.25?3.0 v) or 22 mhz (v dde = 3.0?3.6 v) to meet the timing specification for t jov of [0.2 x t jcyc ] as outlined in the ieee-isto 5001-200 3 specification. ?t cyc 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8?ns 11 tdi, tms data hold time t ntdih, t ntmsh 5?ns 12 tck low to tdo data valid t jov v dde = 2.25?3.0 v 0 12 ns v dde = 3.0?3.6 v 0 9 ns 13 rdy valid to mcko 5 5 the rdy pin timing is asynchronous to mcko. the timing is guaranteed by design to function correctly. ???? 1 2 3 4 5 mcko mdo mseo evto output data valid
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 32 figure 11. nexus tdi, tms, tdo timing 3.13.4 external bus interface (ebi) timing table 22. bus operation timing 1 spec characteristic and description symbol 40 mhz (ext. bus) 2 56 mhz (ext. bus) 2 66 mhz (ext. bus) 2 unit notes min max min max min max 1 clkout period t c 25.0 ? 17.9 ? 15.2 ? ns signals are measured at 50% v dde . 2 clkout duty cycle t cdc 45% 55% 45% 55% 45% 55% t c 3 clkout rise time t crt ?? 3 ?? 3 ?? 3 ns 4 clkout fall time t cft ?? 3 ?? 3 ?? 3 ns tdo 10 11 tms, tdi 12 tck
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 33 5 clkout positive edge to output signal invalid or hi-z (hold time) external bus interface addr[8:31] bdip cs [0:3] data[0:31] oe rd_wr ta tea ts we /be [0:3] t coh 1.0 4 1.5 ? 1.0 4 1.5 ? 1.0 4 1.5 ?ns ebts=0 ebts=1 hold time selectable via siu_eccr[ebts] bit. calibration bus interface cal_addr[10:11, 27:30] cal_cs [0, 2:3] cal_data[0:15] cal_we /be [0:1] t ccoh 1.0 5 1.5 ? 1.0 4 1.5 ? 1.0 4 1.5 ?ns ebts=0 ebts=1 hold time selectable via siu_eccr[ebts] bit. 6 clkout positive edge to output signal valid (output delay) external bus interface addr[8:31] bdip cs [0:3] data[0:31] oe rd_wr ta tea ts we /be [0:3] t cov ? 10.0 4 11.0 ? 7.5 4 8.5 ? 6.0 4 7.0 ns ebts=0 ebts=1 output valid time selectable via siu_eccr[ebts] bit. 6a clkout positive edge to output signal valid (output delay) calibration bus interface cal_addr[10:11, 27:30] cal_cs [0, 2:3] cal_data[0:15] cal_we /be [0:1] t ccov ? 11.0 4 12.0 ? 8.5 4 9.5 ? 7.0 4 8.0 ns ebts=0 ebts=1 output valid time selectable via siu_eccr[ebts] bit. table 22. bus operation timing 1 (continued) spec characteristic and description symbol 40 mhz (ext. bus) 2 56 mhz (ext. bus) 2 66 mhz (ext. bus) 2 unit notes min max min max min max
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 34 7 input signal valid to clkout positive edge (setup time) external bus interface addr[8:31] bdip data[0:31] oe rd_wr ta tea t s w e/be [0:3] t cis 10.0?7.0?5.0?ns 7a input signal valid to clkout positive edge (setup time) calibration bus interface cal_addr[10:11, 27:30] cal_cs [0, 2:3] cal_data[0:15] cal_we /be [0:1] t ccis 11.0?8.0?6.0?ns 8 clkout positive edge to input signal invalid (hold time) external bus interface addr[8:31] bdip data[0:31] oe rd_wr ta tea t s we /be [0:3] t cih 1.0 ? 1.0 ? 1.0 ? ns calibration bus interface cal_addr[10:11, 27:30] cal_cs [0, 2:3] cal_data[0:15] cal_we /be [0:1] t ccih 1.0 ? 1.0 ? 1.0 ? ns 1 ebi timing specified at v dd = 1.35?1.65 v, v dde = 1.6?3.6 v (unless stated otherwise), v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 30 pf with dsc = 0b10. 2 the external bus is limited to half the speed of the internal bus. 3 refer to fast pad timing in ta bl e 1 7 and ta bl e 1 8 (different values for 1.8 v and 3.3 v). 4 the ebts = 0 timings are tested and valid at v dde = 2.25?3.6 v only, whereas ebts = 1 timings are tested and valid at v dde = 1.6?3.6 v. 5 the ebts = 0 timings are tested and valid at v dde = 2.25?3.6 v only, whereas ebts = 1 timings are tested and valid at v dde = 1.6?3.6 v. table 22. bus operation timing 1 (continued) spec characteristic and description symbol 40 mhz (ext. bus) 2 56 mhz (ext. bus) 2 66 mhz (ext. bus) 2 unit notes min max min max min max
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 35 figure 12. clkout timing figure 13. synchronous output timing 1 2 2 3 4 clkout v dde 2 vol_f voh_f 6 5 5 clkout bus 5 output signal output v dde 2 v dde 2 v dde 2 v dde 2 6 5 output signal v dde 2 6
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 36 figure 14. synchronous input timing 7 8 clkout input bus 7 8 input signal v dde 2 v dde 2 v dde 2
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 37 3.13.5 external interrupt timing (irq signals) figure 15. external interrupt timing figure 16. external interrupt setup timing table 23. external interrupt timing 1 1 irq timing specified at f sys = 132 mhz, v dd = 1.35?1.65 v, v ddeh = 3.0?5.5 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 200pf with src = 0b11. spec characteristic symbol min max unit 1 irq pulse-width low t ipwl 3?t cyc 2 irq pulse-width high t ipwh 3?t cyc 3 irq edge-to-edge time 2 2 applies when irq signals are configured for ri sing-edge or falling-edge events, but not both. t icyc 6?t cyc irq 1 2 3 clkout irq 4
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 38 3.13.6 etpu timing figure 17. etpu timing figure 18. etpu input/output timing table 24. etpu timing 1 1 etpu timing specified at f sys = 132 mhz, v dd = 1.35?1.65 v, v ddeh = 3.0?5.5 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 200 pf with src = 0b11. spec characteristic symbol min max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 etpu output channel pulse width t ocpw 2?t cyc 1 2 etpu output etpu input and tcrclk clkout 3 4 etpu output etpu input and tcrclk
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 39 3.13.7 emios (mts) timing 3.13.8 dspi timing table 25. mts timing 1 1 mts timing specified at f sys = 132 mhz, v dd = 1.35?1.65 v, v ddeh = 3.0?5.5 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 50 pf with src = 0b11. spec characteristic symbol min max unit 1 emios (mts) input pulse width t mipw 4?t cyc 2 emios (mts) output pulse width t mopw 1?t cyc table 26. dspi timing 1 spec characteristic symbol 80 mhz 112 mhz 132 mhz unit min max min max min max 1 sck cycle time 2,3 t sck 25 ns 2.9 ms 17.9 ns 2.0 ms 15.2 ns 1.7 ms ? 2 pcs to sck delay 4 t csc 23 ? 15 ? 13 ? ns 3 after sck delay 5 t asc 22 ? 14 ? 12 ? ns 4 sck duty cycle t sdc (t sck 2) ? 2 ns (t sck 2) + 2 ns ??? ?ns 5 slave access time (ss active to sout driven) t a ? 25 ? 25 ? 25 ns 6 slave sout disable time (ss inactive to sout hi-z, or invalid) t dis ? 25 ? 25 ? 25 ns 7 pcsx to pcss time t pcsc 4?4?4?ns 8pcss to pcsx time t pa s c 5?5?5?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) t sui 20 2 ?4 20 ? ? ? ? 20 2 3 20 ? ? ? ? 20 2 6 20 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) t hi ?4 7 21 ?4 ? ? ? ? ?4 7 14 ?4 ? ? ? ? ?4 7 12 ?4 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 5 25 18 5 ? ? ? ? 5 25 14 5 ? ? ? ? 5 25 13 5 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 5.5 8 ?5 ? ? ? ? ?5 5.5 4 ?5 ? ? ? ? ?5 5.5 3 ?5 ? ? ? ? ns ns ns ns
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 40 figure 19. dspi classic spi timing?master, cpha = 0 1 all dspi timing specifications use the fa stest slew rate (src = 0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate. dspi timing is specified at v dd = 1.35?1.65 v, v ddeh = 3.0?5.5 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 50 pf with src = 0b11. 2 the minimum sck cycle time restricts the baud ra te selection for the given system clock rate. these numbers are calculated based on two mpc55xx devices communicating over a dspi link. 3 the actual minimum sck cycle time is limited by pad performance. 4 the maximum value is programmable in d spi_ctarx[pssck] and dspi_ctarx[cssck]. 5 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc]. 6 this number is calculated using the smpl_pt bit field in dspi_mcr set to 0b10. data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 41 figure 20. dspi classic spi timing?master, cpha = 1 figure 21. dspi classic spi timing?slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1)
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 42 figure 22. dspi classic spi timing?slave, cpha = 1 figure 23. dspi modified transfer format timing?master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1)
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 43 figure 24. dspi modified transfer format timing?master, cpha = 1 figure 25. dspi modified transfer format timing?slave, cpha =0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 44 figure 26. dspi modified transfer format timing?slave, cpha =1 figure 27. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 45 3.13.9 eqadc ssi timing figure 28. eqadc ssi timing table 27. eqadc ssi timing characteristics (pads at 3.3 v or 5.0 v) cload = 25 pf on all outputs. pad drive strength set to maximum. spec rating symbol minimum typical maximum unit 2 fck period (t fck = 1 f fck ) 1, 2 1 ss timing specified at f sys = 132 mhz, v dd = 1.35?1.65 v, v ddeh = 3.0?5.5 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 50 pf with src = 0b11. maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 fck duty is not 50% when it is generated through the division of the system clock by an odd number. t fck 2? 17t sys_clk 3 clock (fck) high time t fckht t sys_clk ? 6.5 ? 9 (t sys_clk + 6.5) ns 4 clock (fck) low time t fcklt t sys_clk ? 6.5 ? 8 (t sys_clk + 6.5) ns 5 sds lead / lag time t sds_ll ?7.5 ? +7.5 ns 6 sdo lead / lag time t sdo_ll ?7.5 ? +7.5 ns 7 eqadc data setup time (inputs) t eq_su 22 ? ? ns 8 eqadc data hold time (inputs) t eq_ho 1? ? ns 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 4 5 4 2 3 fck sds sdo external device data sample at sdi eqadc data sample at fck falling-edge fck rising-edge
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 46 3.14 fast ethernet ac timing specifications media independent interface (mii) fast ethernet controller (fec) signals use transistor-to-transistor logic (ttl) signal levels compatible with devices operating at 3.3 v. the ti ming specifications for the mii fec signals are independent of the system clock frequency (par t speed designation). 3.14.1 mii fec receive signal timing fec_rxd[3:0], fec_rx_dv, fec_rx_er, and fec_rx_clk the receive functions corr ectly up to an fec_rx_clk maximum fr equency of 25 mhz plus one percent. there is no minimum frequency require ment. the processor clock frequenc y must exceed four times the fec_rx_clk frequency. table 28 lists mii fec receive channel timings. figure 29 shows mii fec receive signal timings listed in table 28 . figure 29. mii fec receive signal timing diagram table 28. mii fec receive signal timing spec characteristic min max unit 1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns 2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns 3 fec_rx_clk pulse-width high 35% 65% fec_rx_clk period 4 fec_rx_clk pulse-width low 35% 65% fec_rx_clk period m1 m2 fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er m3 m4
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 47 3.14.2 mii fec transmit signal timing fec_txd[3:0], fec_tx_en, fec_tx_er, fec_tx_clk the transmitter functions correctly up to the fe c_tx_clk maximum frequency of 25 mhz plus one percent. there is no minimum fre quency requirement. in addition, the processor clock frequency must exceed twice the fec_tx_clk frequency. the transmit outputs (fec_txd[3: 0], fec_tx_en, fec_tx_er) can be programmed to transition from either the rising- or falling-e dge of tx_clk, and the timing is the same in either case. these options allow the use of non-compliant mii phys. refer to the fast ethernet controller (fec) chapter of the device reference manual for details of this option and how to enable it. table 29 lists mii fec transmit channel timings. figure 30 shows mii fec transmit signal timings listed in table 29 . figure 30. mii fec transmit signal timing diagram table 29. mii fec transmit signal timing spec characteristic min max unit 5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5 ? ns 6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ? 25 ns 7 fec_tx_clk pulse-width high 35% 65% fec_tx_clk period 8 fec_tx_clk pulse-width low 35% 65% fec_tx_clk period m6 fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er m5 m7 m8
mpc5553 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 48 3.14.3 mii fec asynchronous inputs signal timing fec_crs and fec_col table 30 lists mii fec asynchronous input signal timing. figure 31 shows mii fec asynchronous input timing listed in table 30 . figure 31. mii fec asynchronous inputs timing diagram 3.14.4 mii fec serial management channel timing fec_mdio and fec_mdc table 31 lists mii fec serial manageme nt channel timings. the fec func tions correctly with a maximum fec_mdc frequency of 2.5 mhz. figure 32 shows mii fec serial manageme nt channel timings listed in table 31 . table 30. mii fec asynchronous inputs signal timing spec characteristic min max unit 9 fec_crs, fec_col minimum pulse width 1.5 ? fec_tx_clk period table 31. mii fec serial management channel timing spec characteristic min max unit 10 fec_mdc falling-edge to fec_mdio output invalid (minimum propagation delay) 0? ns 11 fec_mdc falling-edge to fec_mdio output valid (maximum propagation delay) ?25 ns 12 fec_mdio (input) to fec_mdc rising-edge setup 10 ? ns 13 fec_mdio (input) to fec_mdc rising-edge hold 0 ? ns 14 fec_mdc pulse-width high 40% 60% fec_mdc period 15 fec_mdc pulse-width low 40% 60% fec_mdc period fec_crs, fec_col m9
electrical characteristics mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 49 figure 32. mii fec serial management channel timing diagram figure 33. reset and c onfiguration pin timing fec_mdc (output) fec_mdio (output) m12 m13 fec_mdio (input) m10 m14 m15 m11 clkout 5 6 reset rstout 6 5
mpc5553 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 50 4 mechanicals 4.1 pinouts 4.1.1 mpc5553 416 pbga pinout figure 34 , figure 35 , and figure 36 show the pinout for the mpc 5553 416 pbga package. while the mpc5553 and the mpc5554/mpc5565/mpc5566 are pin- compatible, the mpc5553 bga is shown to highlight the balls that are not connected to any signal on the mpc5553 (the et pub[0:31] and tsiz[0:1]). the alternate fast ethernet controll er (fec) signals that are multiplexe d with the data bus are not shown for the mpc5553. note some pins have names that include f unctions that are not available on all mpc55 xx devices. for example, ball r25 of the 416 bga package is named ?sina,? but the mpc5553 does not have a dspi a module. in this case, the sina pin can only be used for its al ternate functions of gpio[94] or pcsc[2]. refer to the specific devi ce reference manual for functions available on each device.
mechanicals mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 51 figure 34. mpc5553 416 package no connect. ac22 & ad23 reserved nc_37 vss 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an35 vstby an37 an11 vdda1 an16 an5 vrh an23 an27 an28 vssa0 an15 mdo11 mdo8 vdd vdd33 vss a vdd an32 vss an36 an39 an19 an20 an4 an22 an26 an31 vssa0 an14 mdo10 mdo7 mdo4 mdo0 vss vdde7 b vdd33 an33 vdd vss an8 an17 vssa1 an3 an7 vrl an25 an30 vdda0 an13 mdo9 mdo6 mdo3 mdo1 vss vdde7 vdd c an34 vdd vss an38 an9 an18 an2 an6 an24 an29 an12 mdo5 mdo2 vss vdde7 tck tdi d vdd vdde7 tms tdo test e mseo0 jcomp evti evto f mseo1 mcko g rdy h j vss vss vss vss vdde7 vdde7 vdde7 vdde7 k vss vss vss vss vss vss vss vdde7 l vss vdde2 vdde2 vss vss vss vss vdde7 sinb m bdip vss tea vdde2 vdde2 vss vss vss vss vdde7 soutb pcsb3 pcsb0 pcsb1 n cs3 vss cs2 cs1 cs0 vdde2 vdde2 vss vss vss vss vss pcsa3 pcsb4 sckb pcsb2 p we3 vss we2 we1 we0 vdde2 vdde2 vss vss vss vss vss pcsb5 souta sina scka r vdde2 vdde2 nc_34 rd_wr vdde2 vdde2 vss vdde2 vdde2 vdde2 vss vss pcsa1 pcsa0 pcsa2 vpp t vdde2 nc_35 ta vdd33 vss vdde2 vdde2 vdde2 vdde2 vss vss pcsa4 txda pcsa5 vflash u ts cntxc rxda rstout v rxdb cnrxc txdb reset w vdde2 y extal aa vdde2 vdd xtal ab vdde2 vss vdd vdde2 vdde5 nc_36 vss vdd vrc33 ac vss vdd vdd33 cntxa vdde5 nc_37 vss vdd vdd33 ad br vss vdd oe bg cnrxa vdde5 clkout vss vdd ae vss vdd vdde2 vdde2 nc_38 cntxb cnrxb vdde5 vss af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an10 an21 an0 an1 etrig 1 gpio 205 etrig 0 etpua 30 etpua 31 vddeh 9 vddeh 8 vddeh 1 etpua 28 etpua 29 vddeh 1 etpua 24 etpua 27 etpua 26 etpua 23 etpua 22 etpua 25 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 15 etpua 14 etpua 13 etpua 12 etpua 11 etpua 10 etpua 9 etpua 8 etpua 7 etpua 6 etpua 5 etpua 4 etpua 3 etpua 2 etpua 1 etpua 0 tcrclk a vddeh 6 gpio 204 gpio 203 addr 16 addr 18 addr 17 addr 8 addr 20 addr 19 addr 10 addr 9 addr 22 addr 21 addr 11 addr 24 addr 23 addr 12 addr 13 addr 25 addr 14 addr 15 addr 26 addr 27 addr 31 addr 28 addr 30 addr 29 data 16 data 18 data 17 data 19 data 24 data 21 data 25 data 26 data 20 data 23 data 27 data 28 data 22 gpio 207 gpio 206 data 0 data 29 data 30 data 31 data 8 data 9 data 2 data 4 data 6 data 1 data 3 data 11 data 10 data 13 data 5 data 7 data 15 data 12 data 14 emios 3 emios 1 emios 0 emios 6 emios 5 emios 4 emios 2 emios 10 emios 9 emios 7 emios 8 emios 15 emios 13 emios 11 emios 12 emios 17 emios 16 emios 14 emios 21 emios 22 emios 19 emios 18 emios 23 emios 20 vddeh 4 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk version 2.1 ? 13 july 2004 note: no connects (x = 1 to 38) nc_x ref bypc nc_1 nc_2 nc_3 nc_4 nc_5 nc_6 nc_7 nc_8 nc_9 nc_10 nc_11 nc_12 nc_13 nc_14 nc_15 nc_16 nc_23 nc_27 nc_31 nc_18 nc_19 nc_17 nc_20 nc_21 nc_22 nc_24 nc_25 nc_26 nc_28 nc_29 nc_30 nc_32 nc_33 nc_36
mpc5553 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 52 figure 35. mpc5553 416 package, left side vss 12345678910111213 an35 vstby an37 an11 vdda1 an16 an5 vrh an23 an27 an28 a vdd an32 vss an36 an39 an19 an20 an4 an22 an26 an31 b vdd33 an33 vdd vss an8 an17 vssa1 an3 an7 vrl an25 an30 c an34 vdd vss an38 an9 an18 an2 an6 an24 an29 d vdd e f g h j vss vss vss vss k vss vss vss vss l vss vdde2 vdde2 vss m bdip vss tea vdde2 vdde2 vss n cs3 vss cs2 cs1 cs0 vdde2 vdde2 vss p we3 vss we2 we1 we0 vdde2 vdde2 vss r vdde2 vdde2 nc_34 rd_wr vdde2 vdde2 vss vdde2 t vdde2 nc_35 ta vdd33 vss vdde2 vdde2 u ts v w vdde2 y aa vdde2 ab vdde2 vss vdd vdde2 vss vdd vdd33 br vss vdd oe ae vss vdd vdde2 vdde2 af 12345678910111213 an10 an21 an0 an1 etpua 30 etpua 31 vddeh 1 etpua 28 etpua 29 vddeh 1 etpua 24 etpua 27 etpua 26 etpua 23 etpua 22 etpua 25 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 15 etpua 14 etpua 13 etpua 12 etpua 11 etpua 10 etpua 9 etpua 8 etpua 7 etpua 6 etpua 5 etpua 4 etpua 3 etpua 2 etpua 1 etpua 0 tcrclk a addr 16 addr 18 addr 17 addr 8 addr 20 addr 19 addr 10 addr 9 addr 22 addr 21 addr 11 addr 24 addr 23 addr 12 addr 13 addr 25 addr 14 addr 15 addr 26 addr 27 addr 31 addr 28 addr 30 addr 29 data 16 data 18 data 17 data 19 data 24 data 21 data 25 data 26 data 20 data 23 data 27 data 28 data 22 gpio 207 gpio 206 data 0 data 29 data 30 data 31 data 8 data 9 data 2 data 4 data 6 data 1 data 3 data 11 data 10 data 13 data 5 data 7 ref bypc ad ac no connect. ac22 & ad23 reserved nc_37 version 2.1 ? 13 july 2004 note: no connects (x = 1 to 38) nc_x nc_36
mechanicals mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 53 figure 36. mpc5553 416 package, right side 14 15 16 17 18 19 20 21 22 23 24 25 26 vssa0 an15 mdo11 mdo8 vdd vdd33 vss vssa0 an14 mdo10 mdo7 mdo4 mdo0 vss vdde7 vdda0 an13 mdo9 mdo6 mdo3 mdo1 vss vdde7 vdd an12 mdo5 mdo2 vss vdde7 tck tdi vdde7 tms tdo test mseo0 jcomp evti evto mseo1 mcko rdy vdde7 vdde7 vdde7 vdde7 vss vss vss vdde7 vss vss vss vdde7 sinb vss vss vss vdde7 soutb pcsb3 pcsb0 pcsb1 vss vss vss vss pcsa3 pcsb4 sckb pcsb2 vss vss vss vss pcsb5 souta sina scka vdde2 vdde2 vss vss pcsa1 pcsa0 pcsa2 vpp vdde2 vdde2 vss vss pcsa4 txda pcsa5 vflash cntxc rxda rstout rxdb cnrxc txdb reset extal vdd xtal vdde5 nc_36 vss vdd vrc33 cntxa vdde5 nc_37 vss vdd vdd33 bg cnrxa vdde5 clkout vss vdd nc_38 cntxb cnrxb vdde5 vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 14 15 16 17 18 19 20 21 22 23 24 25 26 etrig 1 gpio 205 etrig 0 vddeh 9 vddeh 8 vddeh 6 gpio 204 gpio 203 data 15 data 12 data 14 emios 3 emios 1 emios 0 emios 6 emios 5 emios 4 emios 2 emios 10 emios 9 emios 7 emios 8 emios 15 emios 13 emios 11 emios 12 emios 17 emios 16 emios 14 emios 21 emios 22 emios 19 emios 18 emios 23 emios 20 vddeh 4 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk nc_1 nc_2 nc_3 nc_4 nc_5 nc_6 nc_7 nc_8 nc_9 nc_10 nc_11 nc_12 nc_13 nc_14 nc_15 nc_16 nc_23 nc_27 nc_31 nc_18 nc_19 nc_17 nc_20 nc_21 nc_22 nc_24 nc_25 nc_26 nc_28 nc_29 nc_30 nc_32 nc_33
mpc5553 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 54 4.1.2 mpc5553 324 pbga pinout figure 37 is a pinout for the mpc5553 324 pbga package. figure 37. mpc5553 324 package vss 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an28 vdd vstby an37 an11 vdda1 an1 an5 vrh vrl an27 an35 vssa0 mdo10 mdo8 vdd vdd33 vss a vdd33 an31 vss vdd an36 an39 an19 an0 an23 an26 an32 vssa0 mdo9 mdo7 mdo4 mdo0 vss vdde7 b an30 vss vdd an8 an17 an21 an3 an7 an22 an25 an33 vdda0 an14 mdo5 mdo2 mdo1 vss vdde7 vdd c an29 vss vdd an38 an10 an18 an2 an6 an24 an15 mdo6 vss vdde7 tck tdi d vdde7 tms tdo test e vdde7 jcomp evti evto f rdy g vss vss vss vss vss vdde7 vss vss vss vss vss vss vss vss vss vss vss vss sinb h vss vdde2 vdde2 vss vss vss soutb pcsb3 pcsb0 pcsb1 j vss vss vss vdde2 vss vss pcsa3 pcsb4 sckb pcsb2 k vss vss vss vdde2 vss vss pcsb5 souta sina scka l bdip cs1 cs0 pcsa1 pcsa0 pcsa2 vpp m cs2 we1 we0 pcsa4 txda pcsa5 vflash n rd_wr cntxc rxda rstout p rxdb cnrxc txdb reset r ts t extal u vdde2 vdd xtal v vss vdd vdde2 vdde5 nc vss vdd vrc33 w vss vdd cntxa vdde5 nc vss vdd vdd33 y vss vdd cnrxa vdde5 clkout vss vdd aa vss vdd vdde2 vdde2 cntxb cnrxb vdde5 vss ab a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an9 an20 an16 vssa1 etpua 28 etpua 29 etpua 25 etpua 24 etpua 27 etpua 23 etpua 22 etpua 17 etpua 20 etpua 19 etpua 14 etpua 13 etpua 16 etpua 15 etpua 10 vddeh 1 etpua 6 gpio 204 gpio 203 vddeh 10 addr 16 addr 17 addr 18 addr 19 addr 20 addr 21 addr 12 addr 22 addr 23 addr 13 addr 25 addr 31 addr 15 addr 26 addr 24 addr 30 addr 28 addr 27 addr 29 data 0 data 1 data 8 data 3 data 9 data 4 data 13 gpio 206 data 5 data 10 data 11 data 12 data 14 data 15 data 7 emios 6 emios 2 emios 10 emios 15 vddeh 4 emios 12 emios 17 emios 16 emios 14 emios 22 emios 19 emios 18 emios 23 emios 20 emios 21 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk version 2.2p ? 13 july 2004 note: no connect. reserved (w18 & y19 are shorted to each other) nc w y aa ab mdo11 an12 an4 ref bypc an13 etpua 30 etpua 31 etpua 26 etpua 21 etpua 18 an34 vddeh 9 mdo3 etpua 11 etpua 12 etpua 2 etpua 7 etpua 8 etpua 0 tcrclk a etpua 3 etpua 4 etpua 9 etpua 5 etpua 1 mcko mseo0 mseo1 cs3 vdd33 ta vdde2 addr 14 vdde2 vdd33 emios 8 vdde2 vdde2 vdde2 gpio 207 data 2 data 6 emios 13 emios 9 emios 5 emios 3 oe emios 11 emios 7 emios 4 emios 1 emios 0 vrc vss
mechanicals mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 55 4.1.3 mpc5553 208 map bga pinout figure 38 is a pinout for the mpc55mpc5553 208 map bga package. notes v ddeh10 and v ddeh6 are connected internally on the 208-ball package and are listed as v ddeh6 . figure 38. mpc5553 208 package vss 12345678910111213141516 an9 an11 vdda1 vrh vrl an12 mdo2 mdo0 vdd33 vss a vdd vss an38 an21 an0 an4 an22 an25 vdda0 an13 mdo3 mdo1 vss vdd b vss an17 an34 an16 an7 an23 an32 an33 an14 an15 vss mseo0 tck c vss an18 an2 an24 an31 an35 vss tms evto test d vdde7 tdi evti mseo1 e tdo mcko jcomp f soutb g vss vss vss vss vss vss vss vss vss vss vss vss pcsb1 h vss vss vss vss pcsb5 txda pcsa2 sckb j cntxc rxda rstout vpp k txdb cnrxc reset l rxdb m vss vdd vdd33 vss n vss vdd cntxa vdd vss vrc33 xtal p vss vdd cnrxa cnrxb vdd vss r vss vdd cntxb vdde5 vss t a b c d e f g h j k l m 12345678910111213141516 an6 an3 vssa1 etpua 30 etpua 31 etpua 28 etpua 29 etpua 26 etpua 24 etpua 27 etpua 25 etpua 21 etpua 23 etpua 22 etpua 17 etpua 14 vddeh 4 emios 16 emios 14 emios 15 emios 17 emios 19 emios 18 emios 23 emios 20 emios 12 pll cfg0 boot cfg1 eng clk 8 june 2005p n p r t vssa0 an27 an28 etpua 19 etpua 20 etpua 7 etpua 15 etpua 16 etpua 6 etpua 11 etpua 12 etpua 13 tcrclk a pcsb3 sinb pcsb0 vdd33 oe vdd vdd vdd an5 an1 vstby vdd33 an30 vddeh 9 vddeh 6 pcsb2 pcsb4 pcsa3 etpua 18 an39 ref bypc an37 an36 vddeh 1 cs0 etpua 10 etpua 8 etpua 3 etpua 9 etpua 4 etpua 2 etpua 1 etpua 0 etpua 5 wkp cfg vss syn extal emios 21 emios 22 emios 10 emios 2 emios 8 emios 11 emios 13 emios 6 emios 9 emios 7 emios 3 emios 5 emios 4 emios 1 emios 0 pll cfg1 vrc ctl gpio 207 gpio 206 vdde2 vdd syn vdd
mpc5553 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 56 4.2 package dimensions 4.2.1 mpc5553 416-pin package the package drawings of the mpc5553 416 pin tepbga package are shown in figure 39 . figure 39. mpc5553 416 tepbga package
mechanicals mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 57 figure 39. mpc5553 416 tepbga package (continued)
mpc5553 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 58 4.2.2 mpc5553 324-pin package the package drawings of the mpc5553 324-pin tepbga package are shown in figure 40 . figure 40. mpc5553 324 tepbga package
mechanicals mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 59 figure 40. mpc5553 324 tepbga package (continued)
mpc5553 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 60 4.2.3 mpc5553 208-pin package the package drawings of the mpc5553 208-pin map bga package are shown in figure 41 . figure 41. mpc5553 208 map bga package
mechanicals mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 61 figure 41. mpc5553 208 map bga package (continued)
mpc5553 microcontroller data sheet, rev. 2.0 mpc5553 revision history freescale semiconductor 62 5 mpc5553 revision history table 32 provides a revision history of the mpc5553 data sheet. table 32. mpc5553 revision history revision location(s) substantive change(s) rev. 0 this is the first released version of this document. rev. 1 ta b l e 1 footnote added to freescale part number column. ta b l e 2 footnotes 6, 8, and 9 changed from 1ma to 2ma. figure 39, figure 40, figure 41 second page of package drawings added. figure 37 removed note about pin r1 in the figure and added a note above it instead. rev. 1.1 throughout editorial changes: subscripting, simplifying language.
mpc5553 revision history mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 63 table 33 is the new format for the revision history and changes continue from table 32 . table 33. mpc5553 revision history ( continued) revision author date substantive change(s) rev. 1.1 nh 02/02/07 changes per rd initial review: ? changed the values in ta b l e 1 4 for the h7fa flash pre-program and erase times. typical and initial max values changed. ? typical values ? 16 kbytes: from 265 to 325 48 kbytes: from 340 to 435 64 kbytes: from 400 to 525 128 kbytes: from 500 to 675 ? initial max values ? 16 kbytes: from 400 to 525 48 kbytes: from 400 to 525 64 kbytes: from 500 to 675 128 kbytes: from 1250 to 1800 rev. 1.1 nh 02/06/07 changes per rd second review: ? added figure 3 to show interpolated idd stby values listed in ta b l e 9 . ? ta b l e 9 dc electrical specifications: chan ged wording of footnote 3. spec 28: corrected conditional text error showing wrong frequency. spec 29: deleted frequency information. ? ta b l e 6 fmpll electrical characteristics: grouped (2 x cl) in specs 12 and 13. ? ta b l e 7 power sequence pin status for fast pads, updated paragraph. ? ta b l e 8 power sequence pin status, updated preceding paragraph. ? section 3.7.1, ?input value of pins during por dependent on vdd33 updated paragraph to remove redundancy, ? ta b l e 1 6 flash biu settlings: changed wording of footnote from ?can be changed after analysis and characterization? to ?these values may change after characterization.? ? ta b l e 1 7 and ta bl e 1 8 : deleted the words ?not? from footnote 2. changed from ?this parameter is supplied for reference and is not guaranteed by design and not tested? to ?this parameter is supplied for refere nce and is guaranteed by design and tested.? ? ta b l e 2 2 bus operation timing: specs 5 and 6: corrected format to show the bus timing values for various frequencies with ebts bit = 0 and ebts bit = 1. specs 6 and 7: added the calibra tions signals: cal_addr, cal_we /be , cal_cs , cal_data. ? ta b l e 2 6 dspi timing: added to beginning of footnote 1 ?all dspi timing specifications use the fastest slew rate (src=0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate.? ? ta b l e 2 7 eqadc ss timing characteristics: co mbined footnotes 1 and 2. moved footnotes 1 and 2 to spec 2 and deleted spec 1.
mpc5553 microcontroller data sheet, rev. 2.0 mpc5553 revision history freescale semiconductor 64 rev 2.0 nh 02/07/07 changes per rd sign-off review: ? changed paragraph preceding ta b l e 7 power sequence pin status for the fast pad: from: although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spik es, etc., the state of the i/o pins during power up/down varies depending on power. pr ior to exiting por, the pads are in a high impedance state (hi-z). to: there are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. therefore, the state of the i/o pins during power up/down varies depending on which supplies are powered. ? section 3.7.1, ?input value of pins during por dependent on vdd33 ,? changed from: to avoid accidentally selecting the bypass clock because pllcfg[0:1] and rstcfg are not treated as ones (1s) when por negates, vdd33 must not lag vddsyn and the reset pin power (vddeh6) when powering the device by more than the vdd33 lag specification in ta b l e 6 . vdd33 individually can lag either vddsyn or the reset power pin (vddeh6) by more than the vdd33 lag specification. vdd33 can lag one of the vddsyn or vddeh6 supplies, but cannot lag both by more than the vdd33 lag spec ification. this vdd3 3 lag specification only applies during power up. vdd33 has no lead or lag requirements when powering down. to : when powering the device, vdd33 must not lag vddsyn and the reset power pin (vddeh6) by more than the vdd33 lag specification listed in ta b l e 6 . this avoids accidentally selecting the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are not powered and therefore cannot read the default state when po r negates. vdd33 can lag vddsyn or the reset power pin (vddeh6), but cannot lag both by more than the vdd33 lag specification. this vdd33 lag specification only applies during power up. vdd33 has no lead or lag requirements when powering down. ? ta b l e 2 2 bus operation timing: added the correct pins to the calibration signals: cal_addr[10:11, 27:30], cal_we /be [0:1], cal_cs [0, 2:3], and cal_data[0:15]. added calibration signals to specs 5 and 8. ? corrected the following ebi signals: specs 7 and 8: added the following signals to specs 7 and 8 the ebi section: oe , rd_wr , and bdip . broke out spec 6 clkout posedge to output signal valid into spec 6 for the ebi signals, and spec 6a for the calibration signals, broke out spec 7 input signal valid to clkout posedge into spec 7 for the ebi signals, and spec 7a for the calibration signals. ? section 3.7.3, ?power-down sequence (vrc33 grounded) ? deleted the underscore in ored_por to become ored por. rev 2.0 nh 2/09/07 ta b l e 2 2 bus operation timing: removed references to cal_oe , cal_rd_wr , and cal_ts because they really use the ebi signals oe , rd_wr , and ts on the mpc5553. table 33. mpc5553 revision history ( continued) revision author date substantive change(s)
mpc5553 revision history mpc5553 microcontroller data sheet, rev. 2.0 freescale semiconductor 65 rev 2.0 nh 2/27/07 per rd comments: ta b l e 2 absolute maximum ratings: changed footnote 6 from: keep the negative dc current greater than 0.6 v on etpub[15] and sinb during the internal power-on reset (por) state. to: keep the negative dc current greater than ?0.6 v on etpub[15] and sinb during the internal power-o n reset (por) state. figure 38 mpc5553 208 map bga pinout: deleted two lines referring to the cs [0] signal ball assignment for the 208. rev 2.0 nh 3/1/07 corrected the signal names in section 3.14, ?fast ethernet ac timing specifications ? to include the fec_ prefix for the signal name. waiting on response from jim eifert, randy dees, jeffery hopkins, and bill terry about the following bugs filed against the data sheets: 1474, 1480, 1482, 1483, 181 1, 1815, 1884, 2254, 2419, 2717, 2873 before preparing for final sign-off again. table 33. mpc5553 revision history ( continued) revision author date substantive change(s)
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